1. Field of the Invention
The present invention relates to a MOS device and to a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact.
2. Description of the Related Art
As is known, simultaneous fabrication in a same integrated device of dual-layer polysilicon memory cells and transistors requires removal of the polysilicon layer overlying the dielectric and of the intermediate dielectric layer in the circuitry area, where the transistors or the electrical connection are made, or forming an electrical connection between the first and the second polysilicon layers for the individual transistors.
In particular, U.S. Pat. No. 4,719,184, filed in the name of the present applicant, describes a process, referred to as the double-poly-short-circuited (DPCC) process, which enables short-circuiting between the first and second polysilicon layers. According to the aforesaid process, after deposition of the first polysilicon layer and of an interpoly-dielectric layer, part of the interpoly-dielectric layer is removed in the circuitry area, using a purposely designed mask referred to as “matrix mask”. This mask enables removal of all of the interpoly dielectric on top of the active area of the transistors, or in preset portions, on top of or outside the active area. In this way, when the second polysilicon layer is deposited, it directly contacts the first polysilicon layer where the interpoly dielectric has been removed.
According to a further possibility, the electrical connection between the first and second polysilicon layers is obtained using a connection region, the production of which requires two masking and etching steps. In fact, first it is necessary to remove part of the second polysilicon layer and of the interpoly-dielectric layer so as to expose part of the first polysilicon layer, and then to open the vias through the passivation layer, for forming the connection region.
The above solution is represented in FIGS. 1 and 2, which illustrate, respectively, a top view and a cross-section of a MOS transistor obtained using the process described. In FIGS. 1 and 2, a body 1, of semiconductor material, has an insulation region 2 surrounding an active area 3 (FIG. 1). A stack 4 extends on top of the body 1 and comprises (FIG. 2): a gate-oxide region 5; a poly1 region 6; an interpoly-dielectric region 7; a poly2 region 8; and a silicide region 9. Spacing regions 10 are formed at the sides of the stack 4, and a passivation layer 11 extends on top of the body 1. A plug 12 extends through the passivation layer 11 as far as the stack 4.
FIG. 1 moreover illustrates the shape of the mask that enables forming the first hole, which has an opening 15 that allows the removal of a portion of the silicide region 9, the poly2 region 8, and the interpoly region 7. Thus, these regions have a width smaller than the poly1 region 6, as may be seen in the cross-section of FIG. 2. FIG. 1 moreover illustrates a subsequent mask having, i.e., an opening 12a for the plug 12, which is staggered with respect to the opening 15, and in particular is set on top of both of the remaining portions of the silicide region 9 and the poly2 region 8 and on top of the portion of the poly1 region 6 not overlaid by the silicide region 9 and the poly2 region 8 to ensure the polysilicon regions 6, 8 to be electrically connected by the plug 12. The plug 12 thus has a step at the silicide layer 9 and, in its bottom part, alongside the regions 7 to 9, has a cross-sectional area much smaller than the top part (on top of the stack 4).
Both for the solution just described and for the solution described in the U.S. Pat. No. 4,719,184, it is disadvantageous that two masks are necessary for electrically connecting poly1 and poly2, and hence the costs of fabrication are high.